This application claims the benefit of Korean Application No. 98-50947, filed Nov. 26, 1998, in the Korean Patent Office, the disclosure of which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a method of detecting a frequency of a digital phase locked loop in an optical disc recording and/or reproducing apparatus which records and/or reproduces data on/from an optical disc, and more particularly, to a digital phase locked loop frequency detection method in which a low clock frequency is used in a digital phase locked loop, to thus obtain a high resolution.
2. Description of the Related Art
A general reproduction apparatus for an optical disc such as a compact disc (CD) or a digital versatile disc (DVD) requires a process of being synchronized with a reproduction signal from the optical disc. A circuit for performing such a process is called a phase locked loop.
A digital phase locked loop (PLL) includes a frequency detection block, a charge pump control block, a charge pump block, a phase detection block, a frequency divider and a voltage controlled oscillator (referred to as a VCO). Here, the charge pump control block performs pulse width modulation of a frequency detection error. The charge pump block generates a current according to the pulse width modulated frequency detection error. The phase locked loop produces a VCO clock signal oscillating at a constant frequency with respect to an input signal, and then varies the frequency of the VCO clock signal, to be synchronized with the input signal. However, since there is a limit in controlling by just a phase control, a difference between a frequency of the VCO clock signal and the frequency of the input signal is calculated to perform a frequency tracking. Then, if the frequency of the input signal becomes close to a frequency band, a phase control is performed. At this time, in order to heighten the resolution and accuracy of the frequency tracking, a clock having a frequency two times or more than that of a reference clock by using a frequency divider is used to count a binary signal, to thereby perform frequency detection.
Thus, since a frequency higher by a desired resolution than the frequency of an actually required clock signal should be used in order to detect the frequency according to conventional art, the frequency detection is performed at the state where a high-frequency signal is used. However, it is difficult to generate a clock frequency of four times or more according to the current technological status. Also, since analog-to-digital conversion limits an allowable clock frequency, in the case of the digital phase locked loop, a high-frequency higher than the reference clock frequency cannot be used.
To solve the above problems, it is an object of the present invention to provide a frequency detection method in a digital phase locked loop which can enhance resolution in detecting a reference signal frequency with only a reference clock frequency, without heightening the reference clock frequency.
Additional objects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
To accomplish the above and other objects of the present invention, there is provided a frequency detection method of an input signal in a digital phase locked loop, the frequency detection method comprising: (a) detecting an edge point of the input signal; (b) sampling a previous and following input signal of the input signal on the basis of the edge point into a predetermined frequency; (c) counting a number of reference clock signals between the detected edge point and a sample which is positioned previously; (d) adding a count value and an interval of time corresponding to the count value to obtain a frequency count value at the edge point; and (e) comparing the obtained frequency count value with a predetermined reference value, and adjusting the frequency according to the comparison result.